TCS ILP test patterns

Normally you will be having 1 + 5 tests for first phase and in the second phase it depends on the stream.

First Phase :

1.Pretest - It covers elementary concepts of scheme programming and basic computer hardware and software. It is all school level questions.. No negative marking in it
Language: Scheme programming and Tool: Dr.Scheme for 4 tests(EC1 to EC4)
2. EC1 - It requires individuals to solve a program in 90 minutes..Questions are simple...Normally 3 questions Marks split up is 25 + 25 + 50. Main focus should be on structures and lists...
3. EC2 - Group of 3 or 4 people are to do projects...Case studies are given and you will have to use scheme programming to do that... Apart from programming you will also have to dram URL, ER Diagrams etc., Marks can be scored.
4. EC3 - Individual problem solving based on OOPS concepts like class,objects...Problem will be simple...Marks can be scored.

5. EC4 - Same group of 3 or 4 people are to do same projects as EC2...Case studies are given and you have to use OOPS concepts in scheme programming to do that... Here you will draw sequence diagram, class diagram etc., marks can be scored....
6. EC5 - By far the toughest and contains around 30 questions of Multiple choice types.Each question carries 1,2 or 3 marks...Negative marking is there for each wrong answer...Most people fail in this...topics for this test are: UNIX(little bit concepts only) and elearning site material contents and whatever theoretical concepts used in your projects... All ec5 questions will be from the elearning portal. Click here to go to elearning portal.

They will take 20% of your ec1, 20% of your ec2, 25% of your ec3, 15%of your ec4, 20% of your ec5 once your ec5 is over. Overall percentage should be above 55%. Otherwise 7 days extension.

Points to be noted : You will have to follow naming conventions in your programming as well as in your projects. Projects should be designed in the user's perspective

What is DDR3 SDRAM?

DIMM with eight DDR3 SDRAM devices.

In electronic engineering, DDR3 SDRAM or double-data-rate three synchronous dynamic random access memory is a random access memory interface technology used for high bandwidth storage of the working data of a computer or other digital electronic devices. DDR3 is part of the SDRAM family of technologies and is one of the many DRAM (dynamic random access memory) implementations.

DDR3 SDRAM is an improvement over its predecessor, DDR2 SDRAM, and the two are not compatible. The primary benefit of DDR3 is the ability to transfer at twice the data rate of DDR2 (I/O at 8× the data rate of the memory cells it contains), thus enabling higher bus rates and higher peak rates than earlier memory technologies. There is no corresponding reduction in latency, as that is a feature of the DRAM array and not the interface. In addition, the DDR3 standard allows for chip capacities of 512 megabits to 8 gigabits, effectively enabling a maximum memory module size of 16 gigabytes.

With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s.

It should be emphasized that DDR3 is a DRAM interface specification; the actual DRAM arrays that store the data are the same as in any other type of DRAM, and have similar performance.